Kaushik B.K., Kumar V.R., Majumder M.K., Alam A. Through Silicon Vias: Materials, Models, Design, and Performance

Taylor & Francis Group, LLC, 2017. — 232 p. — ISBN: 1498745520The conventional two-dimensional integrated circuit (2D IC) packaging technique has almost reached its maximum profitable limit and is no longer useful for future IC integration. With the advancement in technology, the density of dies keeps increasing, and, therefore, the number of input/ output (I/O) pins increases exponentially according to Rent’s rule, and the interconnect length also increases to communicate between the dies. Therefore, due to the limited number of I/O pins and longer interconnects between dies, 2D IC integration offers lower bandwidth and thus degrades system performance. Recent advances in semiconductor technology offer vertical interconnect access (via) that extends through silicon, known as through silicon via (TSV). Compared to the conventional wire bond, TSVs offer higher bandwidth and density with low latency, and power dissipation, thereby enabling higher integration density and superior system performance. The use of TSVs is the only way to overcome the difficulties of 2D packaging issues while extending the momentum of Moore’s law for future very-large-scale integration (VLSI) technology by using the advanced packaging chips named as three-dimensional (3D) chips.Three-Dimensional Technology and Packaging Techniques
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